Achronix Semiconductor Corporation

Achronix CAD Environment (ACE) enables users to map their designs into Achronix FPGA devices. Working together seamlessly with industry standard third party synthesis and simulation tools, ACE offers a complete design environment for Achronix FPGAs.

From design entry to bitstream generation, the Achronix philosophy is to employ tools and design methodologies already familiar to FPGA users. Offering a simple Graphical User Interface for novice users, or a comprehensive script mode for power users, ACE provides a familiar environment for all designers.

The above design flow uses the Achronix CAD Environment in conjunction with third party EDA tools.

Synthesis supported by:

• Synplify Pro™ from Synopsys
• Precision Synthesis™ from Mentor Graphics

Simulation supported by:

• Modelsim™ from Mentor Graphics
• Riviera™ from Aldec

Place and route, timing simulation and bitstream download are performed by the ACE tools.

The following steps are used when implementing a design with the Achronix tool chain.

• The user chosen synthesis tool reads in the Register Transfer Level (RTL) code and any user defined synthesis constraint files
• A technology-mapped netlist is produced
• A project is created in ACE and the technology-mapped netlist is added to the project along with any placement and timing constraints
• The ACE tools convert the design to take advantage of the picoPIPE technology creating a prepared netlist
• Timing analysis can be performed on the prepared netlist (optional)
• The design is placed and routed
• Timing analysis can be performed on the post place and route netlist (optional)
• The routed design can be viewed, and the placement and routing can be analyzed. Analysis capability includes highlighting of critical paths in a physical view of the device
• Finally, the bitstream is generated by ACE and can be downloaded into the FPGA