Speedster7t FPGAs

The Speedster7t FPGA family is optimized for high-bandwidth workloads and eliminates the performance bottlenecks associated with traditional FPGAs. Built on the TSMC 7nm FinFET process, Speedster7t FPGAs feature a revolutionary new 2D network-on-chip (2D NoC), an array of new machine learning processors (MLPs) optimized for high-bandwidth and artificial intelligence/machine learning (AI/ML) workloads, high-bandwidth GDDR6 interfaces, 400G Ethernet and PCI Express Gen5 ports. The 2D NoC connects all of the interfaces to over 80 access points in the FPGA fabric to deliver ASIC-level performance while retaining the full programmability of FPGAs. Get started today with the VectorPath accelerator card, featuring the Speedster7t FPGA.

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2D Network on Chip (2D NoC)	High-Speed Data Interfaces	Machine Learning Processors (MLPs)
>20 Tbps bandwidth Interconnects, I/O, memory, internal functional blocks and FPGA fabric. Reduces routing congestion vs. traditional FPGAs by over 40% Simplifies FPGA design	PCIe Gen5 112 Gbps SerDes channels 400G Ethernet GDDR6 memory Up to eight controllers Up to 4 Tbps bandwidth	Native support for integer, floating point, bfloat16 and block floating point Speeds up to 750 MHz with co-located block RAM Fully fracturable integer multiplier/accumulator
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Speedster7t Product Table

Feature	AC7t800	AC7t1400⁽¹⁾	AC7t1500
Logic Density
System Logic Cells (SLCs)	730k	1,546k	1,546k
6-Input Look-Up Tables (LUTs)	326k	692k	692k
Machine Learning Processors⁽²⁾
32-bit (INT)⁽³⁾	864	2,560	2,560
16-bit (FP or TensorFlow bFloat)⁽⁴⁾	1,728	5,120	5,120
24-bit (FP)	1,728	5,120	5,120
16-bit (INT)	3,456	10,240	10,240
8-bit/6-bit (INT or FP)	13,824	40,960	40,960
4-bit (INT or Block FP)	27,648	81,920	81,920
On-Chip Memory
Total Memory	86 Mb	195 Mb	195 Mb
Local RAM (LRAM) Blocks (2.3 kb)	864	2,560	2,560
Block RAM (BRAM) Blocks (72 kb)	1,152	2,560	2,560
High-Performance Interfaces
112 Gb SerDes	24	32	32
DDR4/5 Memory Channels	1 (DDR4/DDR5)	1 (DDR4)	1 (DDR4)
GDDR6 Memory Channels	6 (1.5 Tbps)	16 (4 Tbps)	16 (4 Tbps)
PCIe (Gen5)	1 (×16)	1 (×8)	1 (×8 or ×16)
Ethernet (10 Gbps to 400 Gbps)	8 lanes 2 × 400G (max)	16 lanes 400G (max)	16 lanes 2 × 400G (max)
Security
Inline Cryptography (25G)	Hard IP	None	Soft IP
Performance
2D NoC bandwidth (Tbps)	12	21	21
ML TOps: INT-8 or bFloat-16⁽⁵⁾	20.5	61	61
Packaging
42.5 × 42.5 mm BGA	1,936 balls	–	–
52.5 × 52.5 mm BGA	–	2,597 balls	2,597 balls
Table Notes AC7t1400 SerDes total device bandwidth limited to 500 Gbps Resources per number format INT – Integer FP – Floating point ML – Machine learning

Next-Generation FPGAs from Achronix

The next generation of Achronix FPGA technology brings many innovations to the FPGA industry including:

Power and performance optimized 2D NoC technology providing fast data transport across the entire FPGA and die-to-die interconnects
Enhanced DSP and ML processor arrays offering low-power, high-performance compute capabilities
New, state-of-the-art, security and encryption features to enable fully secure programming and communication protocols
Support for the highest performance SerDes (up to 112 Gbps), Ethernet (2 x 400 GE) and PCIe (Gen5)
Support for the highest bandwidth external memory interfaces (GDDR6 and DDR5)

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Title	Description	Version	Released Date	Document File
Speedster7t GDDR6 User Guide (UG091)	The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces. This guide provides the details for implementing the GDDR6 IP in custom designs.	3.1	09/03/2024	Download
Speedster7t FPGAs Product Brief (PB033)	The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.	2.1	05/15/2024	Download
Speedster7t FPGA Datasheet (DS015)	The Achronix 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.	1.10	01/08/2024	Download
Speedster7t Clock and Reset Architecture User Guide (UG083)	This document explains the architecture of the different clock networks in a Speedster7t FPGA and and provides information on how to use the clocks.	1.2	07/18/2022	Download
Speedster7t Power User Guide (UG087)	This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.	1.5	01/11/2022	Download
Speedster7t Machine Learning Processor User Guide (UG088)	The machine learning processor block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available.	0.9	08/12/2019	Download

Webinar	Title	Published Date
Click to Register	The Rise of the DPU Dive into the evolving world of Data Processing Units (DPUs) in our latest LinkedIn Live webinar, featuring industry experts Baron Fung (Dell’Oro), Scott Schweitzer (Achronix), and Patrick Kennedy (ServeTheHome). Explore the significant rise of DPUs and their impact on data center infrastructure, networking, and security. Our panelists discuss the current state, market trends, technological advancements, and future outlook of DPUs.	03/29/2024
Click to Register	Unlock the Full Potential of FPGAs for Real-Time ML Inference In this presentation, presented by Bill Jenkins, Director of Product Marketing for AI/Military/Financial, using the example of automatic speech recognition (ASR), we will explore how FPGAs can be used to accelerate conversational AI and Natural Language Processing applications.	01/30/2023
Click to Register	Unlocking the Full Potential of FPGAs for Real-Time ML Inference In this webinar, Achronix Sr. Manager of Product Planning, Salvador Alvarez, presents "Unlocking the Full Potential of FPGAs for Real-Time ML Inference – Tuning an Overlay to an Architecture". In this presentation, using the example of automatic speech recognition (ASR), we will explore how an overlay can be used to optimally leverage the potential performance of an FPGA architecture.	09/22/2022
Click to Register	The Rise of the SmartNIC In this webinar, Scott Schweitzer, Achronix Director of SmartNIC Product Planning and Jon Sreekanth, CTO of Accolade discuss: SmartNIC architecture for 100GbE and beyond Why the Data Plane needs to be dynamically programmable The distinction between packet and flow functions Why simply adding a sea of Arm cores in the Data Plane will not scale The need for a highly performant on-chip network	08/25/2022
Click to Register	Managing FPGA Resources as Virtualized Accelerator Blocks Achronix Semiconductor's presentation reviews how FPGA and embedded FPGA (eFPGA) IP resources can be utilized to provide support for various acceleration offload requirements including protocol translation, security and ML workloads. After attending this presentation, you will understand the benefits of FPGA and eFPGA IP architectures and how they can be used to implement virtualized accelerator blocks in your design.	05/16/2022

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