Achronix Semiconductor Corporation

Achronix FPGAs are packed full of world-class technology, including the unmatched 1.5 GHz picoPIPE™ acceleration technology and world-class 10 Gbps SerDes. Achronix FPGAs consist of a traditional synchronous frame surrounding a picoPIPE logic fabric.

Leveraging picoPIPE technology for the FPGA fabric has two major benefits compared with a traditional fabric. First, when a design is mapped into the picoPIPE fabric, it can be pipelined automatically. Any circuit that will benefit from manual pipelining can automatically achieve increased performance when mapped into picoPIPE technology. Second, the need for global clocks has been removed. picoPIPE technology uses very fine grained local clocking to ensure data can travel at very high speeds.

The high-performance fabric is complemented by the Achronix FPGA frame, which includes configurable I/Os, SerDes, clocks, and PLLs. The frame provides all off-chip interfaces and forms the boundary between the picoPIPE core and these interfaces.

Containing up to 40 lanes of 10 Gbps SerDes, the Speedster^® family offers the highest SerDes bandwidth available in an FPGA today, and enables an aggregate SerDes bandwidth of 800 Gbps.

Speedster FPGAs include four embedded DDR1/2/3 controllers, each offering up to 72 bits of data at 1066 Mbps. Having embedded controllers saves valuable programmable resources and alleviates design challenges related to DDR implementation. The DDR controllers are fully by-passable so the pins can be used as general I/O if the DDR controllers are not needed.

Achronix non-SerDes I/Os are among the fastest in the industry. With performance of up to 1000 Mbps (or 1066 Mbps for DDR3) Achronix I/Os ensure data can be shifted into and out of the picoPIPE fabric fast enough to keep up with the 1.5 GHz internal throughput.