Ausdia, Inc

Partner Details

Ausdia, Inc
830 Stewart Drive Suite 257, Sunnyvale, CA 94085

Partner Overview

Ausdia Inc. is an experienced, trusted technology company solving design's toughest problems and transforming SoC design. The company is focused on delivering proven design constraint development and verification solutions that complement all implementation and timing signoff flows. Ausdia's groundbreaking approach represents a new way for STA developers and users to enable massive productivity gains across the design flow resulting in shrinking design time which ultimately leads to a significant saving in design costs. Founded in 2006, Ausdia has a combined experience of over 60 years in EDA development, chip engineering and methodology.

Ausdia's flagship platform – TimevisionTM – allows STA engineers to dramatically increase their productivity by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data. Timevision brings this same capability to RTL designers, who are often under extreme pressure to be involved with timing closure (but lack the time available to dive into gate-level issues). The platform also assists implementation engineers in trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).


  • Timevision – Constraints Module: Auto generation: generate primary clocks, generated clocks, clock groups etc. Linting: Syntax related, missing objects, wrong options etc. Verification: Verify the constraints and 200+ rules will identify constraints related issues. Transform and Translate constraints: RTL <-> Gate. Auto waiver generation
  • Timevision – Formal Exception verification: Proves if False Path [FP] and Multi-Cycle Path [MCP] applied are correct or incorrect using formal techniques. Generates SVAs that can be used in simulation. Integrated HTML and Waveform reports
  • Timevision – Mode Merge: Merge “N” Mode SDC into “1” SDC. Reduction in compute resource and STA license usage. Clock conflict handling, Case conflict handling etc. Fully correlated, “merged” mode VS each “source” mode. Usage: Synthesis, P&R, STA, Timing ECO
  • Timevision – Hierarchical Constraints Propagation & Integration: Identifies mismatches between “Top” and “Block/IP” level constraints. Ensures alignment between “Top” and “Block/IP” implementation through the project cycle. Pull-up and integrate constraints from “Blocks/IPs” to the SoC toplevel. Push-down constraints from SoC toplevel to “Blocks/IPs”. Incremental mode or complete from scratch mode. Automates constraints integration nightmare for complex SoCs. Enables Block/IP consolidation into larger super-blocks/subsystems for implementation
  • Timevision – IO Budget Generation: SDF Delay Based: Accurate IO budgets based on actual delays, improves PPA. Percentage Based: Fixed percentage based, initial IO budgets early in the project phase. Logic Level Based: Budgeting based on the logic level depth after initial synthesis
  • Timevision – Multi Mode Coverage: Verify if all timing endpoints/startpoints are covered in at least one signoff timing mode. Simultaneously loads all the modes constraints, analyses, and reports missing coverage
  • Timevision – CDC: Block, Fullchip – RTL or Gate. Flat and Hierarchical CDC. Supports Multimode CDC analysis with multiple clocks propagating. Automated clock grouping and exclusions. Full Synchronization, Reset and Formal analysis. Aligned to signoff STA to ensure accuracy. Rich Waiver Support, Waiver backtrack. RDC
  • Timevision – ETM App: Generate, Verify, Query , Edit and Compare ETMs
  • Timevision – Change Analysis: Compares two different designs and generates mismatch report. Compares two different constraints versions and generates mismatch report. Also RTL or golden SDC vs Tool generated SDC. Impact driven analysis and reporting of design and constraint changes
  • Timevision – DFT: Verify the DFT aspects of the design like missing Lock-Up latches etc. TCK Mapping: Full chip TCK Assignment Analysis, Async(func) -> Sync (test), and vice-versa
  • Timevision – Glitch: Ensures static formal techniques to ensure asynchronous signals cannot cause logical glitches. Identifies logical transformations introduced by synthesis or place-and-route that can allow for glitch problems to be introduced into circuit layouts

Partnership Solutions