Introduction to Partial Reconfiguration

This introductory overview of the Achronix Partial Reconfiguration (PR) flow showcases the advantage of the Speedster7t FPGA architecture utilizing the 2D NoC to easily replace, move or scale IP blocks throughout the FPGA fabric without the need to recompile or power down the rest of the FPGA.

Our Director of Product Marketing, Bill Jenkins, walks you through the procedure to create multiple PR bitstreams by creating keep-out zones, compiling the different RTL that resides in those zones to create individual bitstreams, creating a top-level bitstream that incorporates each of the IP blocks in an overall FPGA design, and finally how to dynamically program and swap each of the IP blocks during runtime.

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