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Title Description Version Released Date Document File
Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.

1.1 Download
AI Benchmarking on Achronix Speedster®7t FPGAs (WP999)

Deployments of machine learning networks with auto-regressive critical paths, or recurrence, often poorly utilize AI accelerator hardware. Such networks, like those used in automatic speech recognition (ASR), must run with low latency and deterministic tail-latency for at-scale real-time applications. In this paper, the team at presents an overlay architecture for an inference engine which is then implemented on a Speedster7t FPGA. The team further highlights the benefits of the AI-optimized Speedster7t architecture for low-latency, real-time applications.

1.0 Download
5G Advanced and 6G Evolution Powered by FPGA Technology (WP031)

5G, 5G Advanced, and 6G bring many technical and commercial challenges that need to be met if the promised benefits of this new cellular technology are to be truly achieved. Any solution in this space must deal with the evolving specifications — FPGA and eFPGA IP technology is critical to the successful deployment of these next-generation network technologies.

1.0 Download
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration.

1.3 Download
The Achronix Integrated 2D NoC Enables High-Bandwidth Designs (WP028)

Devices aimed at addressing modern algorithm acceleration workloads must be able to efficiently move high-bandwidth data streams between high-speed interfaces and throughout the device. Achronix Speedster®7t FPGAs can process these high-bandwidth data streams via an integrated new and highly innovative two-dimensional network on chip (2D NoC). This white paper discusses two methods of implementing a 2D NoC and presents an example design to show how the Achronix 2D NoC improves performance, reduces area, and reduces design time when compared to a soft 2D NoC implementation.

1.1 Download
Title Description Version Released Date Document File
Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

2.1 Download
Speedster7t FPGA Datasheet (DS015) The Achronix 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. 1.10 Download
Speedcore eFPGA Datasheet (DS012)

Achronix Speedcore embedded FPGA (eFPGA) IP includes look-up-table, memory, and DSP blocks. Each of these blocks are designed to be modular to allow the definition any mix of resources required for a custom end system.

2.1 Download
Title Description Version Released Date Document File
Using Encrypted Source Files with ACE (AN008)

Designers need a way to protect their source IP, and that is often achieved by way of encrypted RTL. The Achronix tool flow using ACE and Synplify Pro supports the use of encrypted IP to enable protection of all or part of an IP's RTL.

1.1 Download
PCIe Enumeration of Speedster7t FPGAs (AN027)

This Application Note provides the steps to attain enumeration from a non-enumerated device with a PCIe interface and from an already enumerated device.

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Migrating to Achronix FPGA Technology (AN023)

Many users transitioning to Achronix FPGA technology are familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences is necessary to achieving the very best performance and quality of results (QoR).

1.1 Download
Coding Guidelines for Speedcore eFPGAs (AN003)

This application note details certain specific design elements that, with certain coding constructs and constraints, can improve timing performance or lower resource utilization.

2.1 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Runtime Programming of Speedster FPGAs (AN025)

This application note demonstrates changing the I/O ring configuration registers of a Speedster FPGA while in user mode.

1.0 Download
Title Description Version Released Date Document File
Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

2.1 Download
Bluespec RISC-V Soft Processors for Achronix FPGAs (PB038)

Bluespec, Inc., offers a portfolio of RISC-V processors provided as soft-IP for use in Achronix Speedster®7t FPGAs.

1.0 Download
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

2.0 Download
Accelerated Network Infrastructure Code Product Brief (PB037)

The Achronix Accelerated Networking Infrastructure Code (ANIC) is a modular suite of SmartNIC IP blocks optimized for Speedster®7t FPGAs and the VectorPath® Accelerator Card, offering high-performance networking for application acceleration.

1.0 Download
Real-Time ASR Accelerator for Data Centers (PB036)

A real-time automatic speech recognition (ASR) accelerator for data centers, featuring industry-leading WER, concurrent real-time streams, and lowest latency — all running on a single VectorPath accelerator card.

1.1 Download
Title Description Version Released Date Document File
Simulation User Guide (UG072)

The Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist). This guide covers the simulation flow for Achronix devices.

1.6 Download
Synthesis User Guide (UG018)

This user guide describes how to use Synplify Pro from Synopsys to synthesize a design and generate a netlist for implementation in Achronix devices. Suggested optimization techniques are also included.

2.0 Download
ACE User Guide (UG070)

This guide is a reference manual for ACE, used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs.

10.0 Download
Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces. This guide provides the details for implementing the GDDR6 IP in custom designs.

3.0 Download
ACE Installation and Licensing Guide (UG002)

This guide covers software installation and licensing of ACE software under both Windows and Linux operating software.

2.12 Download