Maximize Hardware Assurance with eFPGA IP

In this webinar you will learn how to maximize hardware assurance (HwA) for critical IP in the semiconductor manufacturing process using eFPGA technology. Hardware assurance is of critical importance for manufacturing semiconductors in applications with heightened security requirements. See how eFPGAs can help to reduce the risk of critical IP getting compromised during the entire life cycle of the ASIC including:

  • Obtaining ASIC IP from vendors
  • ASIC design process • ASIC foundry
  • Board design
  • Contract manufacturer
  • PCB storage

By integrating eFPGA IP into an ASIC, critical IP is significantly more secure and exposure to many threats are eliminated. After this webinar, you will understand the challenges in maximizing hardware assurance in the traditional ASIC design process and how adding eFPGAs into your ASIC design will significantly reduce the exposure of critical IP along the ASIC supply chain.

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About the Speaker(s)
Raymond Nijssen

Raymond Nijssen – Vice President and Chief Technologist

Mr. Nijssen has over 20 years of experience in the FPGA and EDA industries in various technical and management positions. Mr. Nijssen joined Achronix as Chief Software Architect to manage the software development group, define the foundations and algorithms of the software system, and architect key aspects of the company’s FPGA architectures. In his current role, he is responsible for the productization of the company’s current products and R&D for new technologies for future products. Prior to Achronix, Mr. Nijssen was at Tabula where he was responsible for placement and timing analysis of a time-multiplexed FPGA technology. Prior to Tabula, he was one of the first engineers at Magma Design Automation, and held multiple leadership positions in charge of routing and placement, data models and customer deployment of Magma’s Blast Plan Pro hierarchy hierarchical virtual prototyping and floorplanning products for very large ASIC designs. Mr. Nijssen received his MSEE degree from Eindhoven University of Technology in The Netherlands, and after that followed its postgraduate program studying EDA for VLSI. He holds several patents related to P&R and asynchronous circuit technologies.