Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC Webinar

The current generation of SmartNICs relies heavily upon utilizing semiconductor devices with many ARM cores (or similar) to process packets at 25GbE. This approach, which is already challenged at 25GbE, becomes even more difficult to scale to 100GbE and higher.

Enter the reconfigurable SmartNIC, a fusion of technologies bound together by a two-dimensional network on chip (2D NoC) overlayed onto a high-performance FPGA fabric.  This webinar will cover five reasons why an FPGA with a 2D NoC is required for the next generation of SmartNICs including:

  • Increasing bandwidth
  • Network virtualization and emerging standards
  • Security and encryption requirements
  • Redefined NVMe storage requirement
  • Design flexibility
     

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About the Speaker(s)
Scott Schweitzer

Scott Schweitzer – Director, SmartNIC Product Planning

Scott has been a lifelong technology evangelist since his baptism on the altar of the TRS-80. He's written profitable software products for Apple's App Store, built hardware, and formally managed programs at IBM, NEC, Myricom, Solarflar, Xilinx, and Achronix. In 2005, Scott shifted his focus to clustering for HPC and extreme performance networking. As 10GbE adoption ramped up, in 2009, he launched his wildly popular 10GbE.net blog, which eventually became the TechnologyEvangelist.co. This blog now sees thousands of monthly page views, and the accompanying podcast has grown in success. As a Director of SmartNIC Product Management, Scott is focused on networking acceleration. He works with customers and partners to recognize opportunities and define new and innovative solutions.