Managing FPGA Resources as Virtualized Accelerator Blocks

Presented by Achronix VP of Architecture, Kent Orthner

Let's talk about embedded FPGAs (eFPGAs)

With the convergence of processing requirements across multiple different industry verticals, the need to support flexibility and scalability in new designs is even more essential. Whilst virtualized/containerized workloads running on CPUs are central to, and simplify many of these new designs, the need for workload acceleration is essential to meet overall power, throughput and latency requirements.

Achronix Semiconductor's presentation reviews how FPGA and embedded FPGA (eFPGA) IP resources can be utilized to provide support for various acceleration offload requirements including protocol translation, security and ML workloads.

Achronix’s unique 2D NoC interconnect allows FPGA fabric resources to be split into logical partitions that appear as a homogeneous block of resources, which can be virtualized into multiple FPGA sub-elements, each supporting its own function. The 2D NoC provides a low latency, transparent conduit between external memory, I/O interfaces and FPGA logic resources. After attending this presentation, you will understand the benefits of FPGA and eFPGA IP architectures and how they can be used to implement virtualized accelerator blocks in your design.

What you’ll learn:

  • The benefits of Speedcore eFPGA IP
  • Data transfer acceleration with high-bandwidth 2D NoC
  • Virtualization & security

 

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About the Speaker(s)
Kent Orthner

Kent Orthner – Vice President of Engineering

Kent Orthner has over 25 years of experience working with working with all aspects of FPGA technology and high-speed silicon connectivity. At Achronix, he leads the development and implementation of our cutting-edge devices and IP solutions. Before Achronix, Kent served as the Vice President of Engineering at Arteris, where he was responsible for all hardware and software development, and where he developed and released the world’s first highly scalable and configurable cache-coherent interconnect IP. Before that, Kent spent 11 years at Altera, leading multiple cross-functional engineering teams, including IP infrastructure, system Integration tools, debug and design visibility tools, and bring-up and regression test infrastructures.   Kent’s expertise and vision drive innovation, ensuring Achronix remains at the forefront of FPGA and accelerator technology. Kent holds a Master of Engineering in Electrical Engineering from Carleton University, Canada, and a Bachelor of Applied Science in Computer Engineering from the University of Ottawa, Canada.