At Achronix, we constantly push the boundaries of innovation to deliver breakthroughs in high-performance FPGA-based data acceleration solutions. Our latest breakthrough comes from leveraging Synopsys Cloud to dramatically enhance our chip design process by reducing full-chip SoC physical verification time from 80 hours to just 16 hours.
We make use of modular clusters with various machine configurations tailored to the various full-chip physical verification jobs we need to run. We have fine-grained control of the throughput of the jobs by dynamically adjusting the compute power and memory resources. This adjustability has enabled us to reduce the run times by 2-3×, allowing us to run more iterations in a given time, thus reducing debugging cycle-time and time needed to converge the design. This capability also enables us to reduce machine and license resources on premise and thereby reduce cost.
Achronix Speedster7t FPGA Integration with Synopsys Cloud Highlights:
- Increased Speed – Achieving 2-3× faster physical verification times has allowed us to expedite our design cycles and improve time-to-market.
- Flexibility and Scalability – Synopsys Cloud's EDA tools and pre-optimized hardware platforms have provided the flexibility and scalability we needed to overcome compute and licensing challenges.
- Enhanced Productivity – With a seamless, browser-based environment and automated license server management, our design teams can now focus more on innovation and less on infrastructure constraints.
Achronix leadership emphasizes that Synopsys Cloud provides a comprehensive design environment for creating system-on-chips (SoCs). With its highly flexible electronic design automation (EDA) tools and scalable computing resources, Achronix is able to produce complete designs more rapidly. This efficiency allows us to enhance their future roadmap schedules, resulting in improved verification processes and higher quality designs delivered ahead of schedule.
Stay tuned for more insights and updates on how we're driving innovation in the semiconductor industry!
Read the full success story on Synopsys' website: https://www.synopsys.com/blogs/chip-design/soc-physical-verification-tool-achronix.html.