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Title Description Version Released Date Document File
The Achronix Integrated 2D NoC Enables High-Bandwidth Designs (WP028)

Devices aimed at addressing modern algorithm acceleration workloads must be able to efficiently move high-bandwidth data streams between high-speed interfaces and throughout the device. Achronix Speedster®7t FPGAs can process these high-bandwidth data streams via an integrated new and highly innovative two-dimensional network on chip (2D NoC). This white paper discusses two methods of implementing a 2D NoC and presents an example design to show how the Achronix 2D NoC improves performance, reduces area, and reduces design time when compared to a soft 2D NoC implementation.

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Reduce Speech Transcription Costs by up to 90% with CAI (WP030)

Conversational artificial intelligence (CAI) uses deep learning (DL), a subset of machine learning (ML), to automate speech recognition, natural language processing and text to speech using machines. Achronix and are teaming up to deliver an ASR platform consisting of a 200W, x16 PCIe Gen4-based accelerator card and the associated software which together can sustain up to 4000 RTS concurrently, processing up to 1 million five-minute transcriptions per 24-hour period — reducing costs by as much as 90% versus cloud-based APIs.

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Achronix FPGAs Optimize AI in Industry 4.0 and 5.0 (WP027)

Industry has come a long way over in the last three hundred years. Machines were first introduced in the 1700s, mainly water and steam driven, introducing the Industrial Revolution in the late 1700s. Automation and computer technology would enter the picture in the late 1960's, paving the way for the eventual automation, artificial intelligence (AI) and networked solutions of today. Although it might appear that humans are no longer in the picture, Industry 5.0 is bringing us full circle by combining the precision and efficiency of robotic systems, driven largely by AI, with the ingenuity and real-time thought of the human mind — all leading to more optimal manufacturing environments.

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FPGAs and eFPGAs Accelerate ML Inference at the Edge (WP026)

With the rapid proliferation of Internet-of-Things (IoT) and billions of connected devices, there is a paradigm shift taking place where big data is not only being processed in the core data center but also at the network edge. Field Programmable Gate Arrays (FPGAs), sitting at the intersection of performance and flexibility, are a promising solution for deep learning edge inference applications.

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Data Orchestration Supports the Next Advance in AI (WP025)

Artificial intelligence (AI) and machine learning (ML) technologies now power a rapidly expanding range of product and applications from deeply embedded systems to hyperscale data-center deployments. Although there is a huge degree of diversity in the hardware designs supporting these applications, all require hardware acceleration. Data orchestration encompasses the pre- and post-processing operations that ensure the data seen by a machine learning engine arrives at an optimal speed and in the most suitable form for efficient processing.

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Title Description Version Released Date Document File
Understanding ACE Timing Reports (AN024)

Accurate timing constraints and proper understanding of timing analysis reports are critical to successful FPGA design projects. This application note introduces ACE users to the structure of ACE timing reports generated during an ACE place-and-route run.

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Speedcore User Interface Timing Sign-off Methodology (AN009)

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.1 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
SoC-Speedcore Interface Tests (AN022)

The input and output paths between the host SoC and a Speedcore instance are an important test component. It is essential to have a structure that ties seamlessly to the SoC's test flow without requiring special functions such as loading a bitstream in the Speedcore instance.

1.0 SoC-Speedcore_Interface_Tests_AN022.pdf
Migrating to Achronix eFPGA Technology (AN014)

Many users transitioning to Achronix eFPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

1.1 Migrating_to_Achronix_eFPGA_Technology_AN014.pdf
ACE ECO Flow Guide (AN015)

This tutorial serves as an introduce to the ACE engineering change order (ECO) suite — a set of Tcl commands that can add or remove instances, nets, pin connections, and more from a placed-and-routed design.

1.0 ACE_ECO_Flow_Guide_AN015.pdf
Title Description Version Released Date Document File
VectorPath S7t-VG6 Accelerator Card

Developed jointly with BittWare, the VectorPath® S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

2023.06.05 Download
Achronix Company Backgrounder (PB029)

Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market.

1.6 Download
Achronix Tool Suite (PB002)

The Achronix Tool Suite works in conjunction with industry-standard synthesis tools, allowing FPGA designers (for both standalone and embedded) to easily map their designs into Achronix FPGA technology. Achronix provides ACE together with an Achronix-optimized version of Synplify Pro from Synopsys, the industry standard for producing high-performance and cost-effective FPGA designs.

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Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

1.0 Download
Speedcore eFPGA Test Chip Evaluation Board (PB030)

The Speedcore eFPGA evaluation board from Achronix contains the 16-nm Speedcore eFPGA test chip. The evaluation board’s Speedcore test chip has been customized with the right blend of resources such as LUTs, BRAMs, DSP64s, DFFs and a number of I/O so as to provide an optimum programmable platform for demonstrating, evaluating and testing Achronix’s Speedcore technology.

1.0 Download
Title Description Version Released Date Document File
Speedster7t Configuration User Guide (UG094)

At startup, Speedster7t FPGAs require configuration via a bitstream. This user guide details the programming process through one of four available interfaces in the FPGA configuration unit (FCU), the logic controlling the configuration process.

2.0 Download
Speedster7t Pin Connectivity User Guide (UG084)

This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines.

1.7 Download
Speedster7t SerDes User Guide (UG099)

This product guide describes the function and operation of the Achronix Speedster7t FPGA SerDes for multi-standard applications and custom configurations.

1.2 Download
Speedster7t Soft IP User Guide (UG103)

This document describes the available soft IP cores and the methods for configuration and instantiation of each.

2.2 Download
Design Flow User Guide (UG106)

This user guide covers various aspects of the Achronix toolchain design flow.

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